The present invention relates to a method of controlling a voltage pulse which is applied in erasing or writing information in a flash memory.
In general, the writing state or erasing state of a flash memory is determined by the level of the threshold voltage of its memory cell. There are two cases in which the level of the threshold voltage is used differently for determining the state of the flash memory. In one case, the state at a high threshold voltage is used as the writing state, while the state at a low threshold voltage is used as the erasing state. In the other case, the state at a low threshold voltage is used as the writing state, while the state at a high threshold voltage is used as the erasing state, contrary to the former case.
FIG. 3 shows the distribution of the threshold voltages of a plurality of memory cells which were written or erased under the same conditions when the state at a high threshold voltage is used as the writing state and the state at a low threshold voltage is used as the erasing state. In FIG. 3, the horizontal axis designates variations in threshold voltage of the memory cells, while the vertical axis designates the number of the memory cells. The level of the threshold voltage of each memory cell can be changed by applying a voltage pulse to the memory cell, and by changing the direction, magnitude, and application time of the voltage pulse, the level of the threshold voltage can be controlled. However, since the characteristics of memory cells constituting the flash memory are different, even when the voltage pulses similarly set are used to erase or write information in the plurality of memory cells at a time, the threshold voltages of the individual memory cells vary accordingly, resulting in the distribution in FIG. 3.
FIG. 4 shows the basic flow of a conventional erase control method when a flash memory having memory cells which are different in characteristics is subjected to a simultaneous erasing operation. As shown in the drawing, the conventional erase control method consists of Steps S11 to S15, which are described below.
Step S11: Each memory cell is programmed prior to erasing. That is, each memory cell is set in the state at a high threshold voltage.
Step S12: Next, the voltage pulse to be applied for erasing data is temporarily set to a specified value.
Step 13: With the application of the voltage pulse, the erasing of data is performed with respect to each memory cell.
Step 14: Verification is carried out so as to check that the threshold voltage of each memory cell that has undergone the erasing operation is sufficiently lowered, i.e., that the erasing operation was performed completely. Specifically, it is examined whether or not the threshold voltage of each memory cell has reached a specified value or under.
If there is at least one memory cell having a high threshold voltage, the procedure returns from Step S15 to S12, where the erasing voltage pulse is reset, so as to perform a re-erasing operation in Step 13 and then execute verification again in Step S14. After repeating the steps of erasing, verification, and the like, if the threshold voltage of memory cells A (see FIG. 3) that are slowest at erasing (i.e., the maximum value of the threshold voltages of the memory cells) has reached the specified value or under, the result of the verification becomes "Yes", thereby completing the erase control.
The setting of the voltage in the verification is controlled by means of a constant voltage circuit disposed in a flash memory or by means of an external apparatus for setting and supplying the voltage to the flash memory. Thus, according to the conventional method, the erase control is performed on the basis of the memory cells having the highest threshold voltage, in view of the variations in threshold voltage of the memory cells. On the other hand, an influence on excessively erased memory cells B, which are fast at erasing as shown in FIG. 3, is not directly detected in the verification. The voltage for verification is set in consideration of the distribution of the threshold voltages of the memory cells B fast at erasing, which was deduced from the threshold voltages of the memory cells A slow at erasing, so as to secure the voltage for reading information from the flash memory.
Since the power-supply voltage of a conventional flash memory is considerably high, the threshold voltages of the memory cells are accordingly high. Therefore, the threshold voltage never reaches an excessively low value after the erasing of the memory, even though the difference in characteristic of the memory cells constituting the flash memory is considered. Consequently, even when the memory cells A slow at erasing are solely checked in the verification without directly checking the memory cells B fast at erasing, the erasing voltage pulse can be set by deducing the distribution of the threshold voltages of the memory cells B, with the result that the memory cells B are never put in the excessively erased state after they were erased. In other words, no consideration is paid to those memory cells having lower threshold voltages.
However, as the power-supply voltage has become lower in recent years, it becomes necessary to lower the threshold voltage. If the conventional erase control method is used to perform a low-voltage operation, however, there arises a possibility that an excessively erased memory cell having a threshold voltage of 0 V or less may be produced, for such an excessively erased memory cell is not detected in the conventional method.
In the excessively erased memory cell having a threshold voltage of 0 V or less, a leakage current is generated. That is, even when the gate voltage is 0 V, a current is allowed to flow between the source and drain. In the case of reading information from a specific memory cell, therefore, if an excessively erased memory cell exists on the same bit line, the information stored in the specific memory cell to be read may be misread under the influence of the leakage current. For example, even when the specific memory cell to be read is in the state at a high threshold voltage, i.e., in High state which does not allow the flow of an electric current, if an excessively erased memory cell exists on the same bit line and the leakage current flows along the bit line, the wrong information that the specific memory cell is in Low state is obtained.
Where is another conventional method in which the state of the memory cell at a high threshold voltage is used for erasing, while the state at a low threshold voltage is used for writing, contrary to the distribution in FIG. 3. In this case also, if the threshold voltage of memory cells that are fastest at writing, i.e., excessively written memory cells reaches 0 V or under, the misreading of information may occur under the influence of the leakage current, similarly to the case shown in FIG. 3.